Hardware and Architecture

Hardware and Architecture — CIE A Level Computer Science 9618

1. CPU Architecture

The Central Processing Unit (CPU) is the brain of the computer. Key components:

Arithmetic and Logic Unit (ALU):

• Performs arithmetic operations (+, −, ×, ÷)
• Performs logical operations (AND, OR, NOT, XOR)
• Performs shift operations (left shift, right shift)
• Contains status/flag register (carry, zero, negative, overflow flags)

Control Unit (CU):

• Manages and coordinates all CPU operations
• Generates control signals to direct data flow
• Interprets instructions and controls the fetch-execute cycle

Registers (ultra-fast storage inside CPU):

| Register | Full Name | Purpose |

|---|---|---|

| PC | Program Counter | Holds address of next instruction to fetch |

| MAR | Memory Address Register | Holds address being accessed in memory |

| MDR/MBR | Memory Data Register | Holds data just read from or about to be written to memory |

| CIR | Current Instruction Register | Holds the instruction currently being decoded/executed |

| ACC | Accumulator | Holds results of ALU operations |

| SR | Status Register | Holds flags (carry, zero, negative, overflow) |

System clock: Generates regular timing pulses. Every operation takes a fixed number of clock cycles. **Clock speed** (MHz/GHz) = cycles per second. Higher clock speed → more instructions per second (generally).

2. The Fetch-Execute Cycle

Every CPU instruction follows this cycle:

Fetch phase:

1. MAR ← [PC] (copy contents of PC to MAR)
2. MDR ← [memory(MAR)] (fetch instruction from memory at address in MAR)
3. PC ← PC + 1 (increment PC to point to next instruction)
4. CIR ← [MDR] (copy instruction from MDR to CIR for decoding)

Decode phase:

1. CU decodes the instruction in CIR (splits into opcode + operand)

Execute phase:

1. Instruction is executed by ALU, CU, or I/O controllers

Interrupts: CPU periodically checks for interrupt signals (from I/O devices, timer, errors). If interrupt: finish current instruction → save state → execute interrupt service routine (ISR) → restore state → resume.

3. Factors Affecting CPU Performance

Clock speed: More cycles per second → faster execution. Measured in GHz. Limit: heat generation.

Number of cores: Multiple cores can execute different program threads simultaneously. Quad-core = 4 independent processors on one chip.

Cache size: Ultra-fast memory between CPU and RAM. L1 cache (fastest, smallest, on chip) → L2 → L3 (largest, slowest, sometimes shared between cores). Larger cache → more instructions/data immediately available → fewer slow RAM accesses.

Bus width: Width of data bus (bits) = amount of data transferred per cycle. 64-bit bus transfers 64 bits at once.

Pipelining: Overlapping fetch-execute cycles. While one instruction executes, the next is decoded and the one after that is fetched. Increases throughput (instructions per second) without increasing clock speed.

Simultaneous Multi-Threading (Hyper-Threading): Each physical core appears as two logical cores to the OS — more efficient use of CPU resources.

4. Memory Hierarchy

| Level | Speed | Size | Cost/Bit | Location |

|---|---|---|---|---|

| Registers | Fastest | Bytes | Highest | Inside CPU |

| Cache (L1/L2/L3) | Very fast | KB–MB | Very high | On/near CPU chip |

| RAM (Main memory) | Fast | GB | Moderate | Motherboard |

| SSD | Moderate | GB–TB | Low | Internal drive |

| HDD | Slower | TB | Very low | Internal drive |

| Optical/Tape | Slowest | GB–PB | Lowest | External/archive |

Principle of locality: Programs tend to access nearby addresses and repeat accesses to recently used data → cache effectiveness.

Virtual memory: OS uses part of HDD/SSD as extension of RAM when RAM is full. Much slower than RAM (involves disk access). **Thrashing:** Excessive swapping between RAM and virtual memory → severe performance loss.

5. Buses

The bus is a shared communication pathway connecting CPU, memory, and I/O.

Three buses:

| Bus | Direction | Carries |

|---|---|---|

| Address bus | CPU → (one-way) | Memory address to access |

| Data bus | Bidirectional | Data being transferred |

| Control bus | Bidirectional | Control signals (read, write, interrupt, clock) |

Address bus width: Determines addressable memory. 32-bit address bus → 2³² = 4 GB maximum address space. 64-bit → 16 exabytes (practically unlimited).

Data bus width: Determines data throughput per transfer. 64-bit data bus = 8 bytes per transfer.

6. Input/Output Devices

Input: Keyboard, mouse, touchscreen, microphone, camera, scanner, barcode reader, sensors.

Output: Monitor (LCD, OLED), printer (inkjet, laser, 3D), speakers, actuators.

I/O interface: Manages communication between CPU and peripheral devices (handles speed differences, data format differences, buffering).

7. Secondary Storage

Hard Disk Drive (HDD):

• Magnetic storage on spinning platters
• Moving read/write head on actuator arm
• Advantages: large capacity, low cost per GB, mature technology
• Disadvantages: mechanical → slower, fragile (drop damage), moving parts wear out

Solid State Drive (SSD):

• Flash memory (NAND) — no moving parts
• Advantages: faster (especially random access), silent, shock-resistant, energy-efficient
• Disadvantages: more expensive per GB, limited write cycles

Optical discs (CD/DVD/Blu-ray):

• Laser reads/writes pits and lands on disc surface
• Used for: software distribution, media archiving, backup

Magnetic tape:

• Very cheap per GB; extremely high capacity
• Sequential access only (no random access)
• Used for: long-term archival backup (disaster recovery)